2013
Kitsos, Paris; Voros, Nikolaos; Dagiuklas, Tasos; Skodras, Athanassios
A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding Proceedings Article
In: 2013 18th International Conference on Digital Signal Processing (DSP), pp. 1-5, 2013, ISSN: 1546-1874.
Abstract | Links | BibTeX | Tags: 2D DCT, distributed arithmetic, FPGA implementation, VHDL, video coding
@inproceedings{Kitsos2013b,
title = {A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding},
author = {Paris Kitsos and Nikolaos Voros and Tasos Dagiuklas and Athanassios Skodras},
doi = {10.1109/ICDSP.2013.6622742},
issn = {1546-1874},
year = {2013},
date = {2013-07-01},
booktitle = {2013 18th International Conference on Digital Signal Processing (DSP)},
pages = {1-5},
abstract = {This paper presents two high performance FPGA architectures for the 2D DCT computation for Ultra High Definition video coding systems. Both architectures use Distributed Arithmetic to perform the necessary multiplications instead of traditional multipliers. The first architecture uses 105 clock cycles to transform an 8×8 block and reaches a rate of up to 206 samples per second at a 338.5 MHz frequency, while the second one requires 65 cycles for each 8×8 block and achieves a rate equal to 252 samples per second at 256 MHz. Both architectures have been implemented using VHDL. Virtex7 FPGA of Xilinx has been used for the realization of both implementations.},
keywords = {2D DCT, distributed arithmetic, FPGA implementation, VHDL, video coding},
pubstate = {published},
tppubtype = {inproceedings}
}
Kitsos, Paris; Sklavos, Nicolas; Provelengios, George; Skodras, Athanassios
FPGA-based performance analysis of stream ciphers ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0 Journal Article
In: Microprocessors and Microsystems, vol. 37, no. 2, pp. 235 - 245, 2013, ISSN: 0141-9331, (Digital System Safety and Security).
Abstract | Links | BibTeX | Tags: Bluetooth, Cryptography, eStream portfolio, FPGA implementation, GSM, LTE, Stream ciphers, UMTS
@article{Kitsos2013bb,
title = {FPGA-based performance analysis of stream ciphers ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0},
author = {Paris Kitsos and Nicolas Sklavos and George Provelengios and Athanassios Skodras},
url = {http://www.sciencedirect.com/science/article/pii/S014193311200169X},
doi = {https://doi.org/10.1016/j.micpro.2012.09.007},
issn = {0141-9331},
year = {2013},
date = {2013-01-01},
journal = {Microprocessors and Microsystems},
volume = {37},
number = {2},
pages = {235 - 245},
abstract = {In this paper, the hardware implementations of six representative stream ciphers are compared in terms of performance, consumed area and the throughput-to-area ratio. The stream ciphers used for the comparison are ZUC, Snow3g, Grain V1, Mickey V2, Trivium and E0. ZUC, Snow3g and E0 have been used for the security part of well known standards, especially wireless communication protocols. In addition, Grain V1, Mickey V2 and Trivium are currently selected as the final portfolio of stream ciphers for Profile 2 (Hardware) by the eStream project. The designs were implemented by using VHDL language and for the hardware implementations a FPGA device was used. The highest throughput has been achieved by Snow3g with 3330Mbps at 104MHz and the lowest throughput has been achieved by E0 with 187Mbps at 187MHz. Also, the most efficient cipher for hardware implementation in terms of throughput-to-area ratio is Mickey V2 cipher while the worst cipher for hardware implementation is Grain V1.},
note = {Digital System Safety and Security},
keywords = {Bluetooth, Cryptography, eStream portfolio, FPGA implementation, GSM, LTE, Stream ciphers, UMTS},
pubstate = {published},
tppubtype = {article}
}