2018
Pyrgas, Lampros; Kitsos, Paris; Skodras, Athanassios
Compact FPGA architectures for the two-band fast discrete Hartley transform Journal Article
In: Microprocessors and Microsystems, vol. 61, pp. 117 - 125, 2018, ISSN: 0141-9331.
Abstract | Links | BibTeX | Tags: Digital signal processing, FPGA architecture, Two-band fast discrete hartley transform, VHDL
@article{Pyrgas2018b,
title = {Compact FPGA architectures for the two-band fast discrete Hartley transform},
author = {Lampros Pyrgas and Paris Kitsos and Athanassios Skodras},
url = {http://www.sciencedirect.com/science/article/pii/S0141933118300358},
doi = {https://doi.org/10.1016/j.micpro.2018.06.002},
issn = {0141-9331},
year = {2018},
date = {2018-01-01},
journal = {Microprocessors and Microsystems},
volume = {61},
pages = {117 - 125},
abstract = {The discrete Hartley transform is a real valued transform similar to the complex Fourier transform that finds numerous applications in a variety of fields including pattern recognition and signal and image processing. In this paper, we propose and study two compact and versatile hardware architectures for the computation of the 8-point, 16-point and 32-point Two-Band Fast Discrete Hartley Transform. These highly modular architectures have a symmetric and regular structure consisting of two blocks, a multiplication block and an addition/subtraction block. The first architecture utilizes 8 multipliers and 16 adders/subtractors, achieving a maximum clock frequency of 95 MHz. The second architecture utilizes only 4 multipliers and 8 adders/subtractors, achieving a maximum clock frequency of 100 MHz; however it requires additional multiplexers and more clock cycles (from 1 to 58 clock cycles depends on the points) for the computation. As a result, the proposed hardware architectures constitute an efficient choice for area-restricted applications such as embedded or pervasive computing systems.},
keywords = {Digital signal processing, FPGA architecture, Two-band fast discrete hartley transform, VHDL},
pubstate = {published},
tppubtype = {article}
}
2016
Pyrgas, Labros; Kitsos, Paris; Skodras, Athanassios
An FPGA design for the two-band fast discrete hartley transform Proceedings Article
In: 2016 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), pp. 295–299, IEEE 2016.
Abstract | Links | BibTeX | Tags: Digital signal processing, Field Programmable Gate Array architecture (FPGA), Two-band fast discrete hartley transform, VHDL
@inproceedings{Pyrgas2016b,
title = {An FPGA design for the two-band fast discrete hartley transform},
author = {Labros Pyrgas and Paris Kitsos and Athanassios Skodras},
url = {https://ieeexplore.ieee.org/document/7886052},
doi = {10.1109/ISSPIT.2016.7886052},
year = {2016},
date = {2016-01-01},
booktitle = {2016 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT)},
pages = {295--299},
organization = {IEEE},
abstract = {The discrete Hartley transform finds numerous applications in signal and image processing. An efficient Field Programmable Gate Array implementation for the 64-point Two-Band Fast Discrete Hartley Transform is proposed in this communication. The architecture requires 57 clock cycles to compute the 64-point Two-Band Fast Discrete Hartley Transform and reaches a rate of up to 103.82 million samples per second at a 92 MHz clock frequency. The architecture has been implemented using VHDL and realized on a Cyclone IV FPGA of Altera.},
keywords = {Digital signal processing, Field Programmable Gate Array architecture (FPGA), Two-band fast discrete hartley transform, VHDL},
pubstate = {published},
tppubtype = {inproceedings}
}
2015
Fotopoulos, Vasileios; Fanariotis, Anastasios; Orphanoudakis, Theofanis; Skodras, Athanassios
Remote FPGA Laboratory Course Development Based on an Open Multimodal Laboratory Facility Proceedings Article
In: Proceedings of the 19th Panhellenic Conference on Informatics, pp. 447–452, ACM, Athens, Greece, 2015, ISBN: 978-1-4503-3551-5.
Abstract | Links | BibTeX | Tags: distance learning, FPGA, online course, remote lab, VHDL
@inproceedings{Fotopoulos2015,
title = {Remote FPGA Laboratory Course Development Based on an Open Multimodal Laboratory Facility},
author = {Vasileios Fotopoulos and Anastasios Fanariotis and Theofanis Orphanoudakis and Athanassios Skodras},
url = {http://doi.acm.org/10.1145/2801948.2801950},
doi = {10.1145/2801948.2801950},
isbn = {978-1-4503-3551-5},
year = {2015},
date = {2015-01-01},
booktitle = {Proceedings of the 19th Panhellenic Conference on Informatics},
pages = {447--452},
publisher = {ACM},
address = {Athens, Greece},
series = {PCI '15},
abstract = {In this paper the implementation of a remote FPGA laboratory course is proposed, based on a low cost but powerful FPGA development board, the ALTERA DE0-Nano which is powered by an Altera Cyclone IV Field Programmable Gate Array (FPGA) IC. The course is developed based on an open multimodal laboratory facility at the Digital Systems and Media Computing Laboratory of the Hellenic Open University. The course consists of laboratory exercises in the form of VHDL (VHSIC Hardware Description Language) design experiments that the end user can conduct from his or her Personal Computer through a graphical web interface and Altera's Quartus II EDA (Electronic Design Automation) software on hardware that is connected and set-up on a remote server while observing the results in real time. The exercises created for this course are designed to be both educational and interesting while being geared towards entry-level users thus producing a trouble-free RL (Remote Laboratory) that in turn maximizes educational gain.},
keywords = {distance learning, FPGA, online course, remote lab, VHDL},
pubstate = {published},
tppubtype = {inproceedings}
}
2013
Kitsos, Paris; Voros, Nikolaos; Dagiuklas, Tasos; Skodras, Athanassios
A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding Proceedings Article
In: 2013 18th International Conference on Digital Signal Processing (DSP), pp. 1-5, 2013, ISSN: 1546-1874.
Abstract | Links | BibTeX | Tags: 2D DCT, distributed arithmetic, FPGA implementation, VHDL, video coding
@inproceedings{Kitsos2013b,
title = {A high speed FPGA implementation of the 2D DCT for Ultra High Definition video coding},
author = {Paris Kitsos and Nikolaos Voros and Tasos Dagiuklas and Athanassios Skodras},
doi = {10.1109/ICDSP.2013.6622742},
issn = {1546-1874},
year = {2013},
date = {2013-07-01},
booktitle = {2013 18th International Conference on Digital Signal Processing (DSP)},
pages = {1-5},
abstract = {This paper presents two high performance FPGA architectures for the 2D DCT computation for Ultra High Definition video coding systems. Both architectures use Distributed Arithmetic to perform the necessary multiplications instead of traditional multipliers. The first architecture uses 105 clock cycles to transform an 8×8 block and reaches a rate of up to 206 samples per second at a 338.5 MHz frequency, while the second one requires 65 cycles for each 8×8 block and achieves a rate equal to 252 samples per second at 256 MHz. Both architectures have been implemented using VHDL. Virtex7 FPGA of Xilinx has been used for the realization of both implementations.},
keywords = {2D DCT, distributed arithmetic, FPGA implementation, VHDL, video coding},
pubstate = {published},
tppubtype = {inproceedings}
}