2018
Pyrgas, Lampros; Kitsos, Paris; Skodras, Athanassios
Compact FPGA architectures for the two-band fast discrete Hartley transform Journal Article
In: Microprocessors and Microsystems, vol. 61, pp. 117 - 125, 2018, ISSN: 0141-9331.
Abstract | Links | BibTeX | Tags: Digital signal processing, FPGA architecture, Two-band fast discrete hartley transform, VHDL
@article{Pyrgas2018b,
title = {Compact FPGA architectures for the two-band fast discrete Hartley transform},
author = {Lampros Pyrgas and Paris Kitsos and Athanassios Skodras},
url = {http://www.sciencedirect.com/science/article/pii/S0141933118300358},
doi = {https://doi.org/10.1016/j.micpro.2018.06.002},
issn = {0141-9331},
year = {2018},
date = {2018-01-01},
journal = {Microprocessors and Microsystems},
volume = {61},
pages = {117 - 125},
abstract = {The discrete Hartley transform is a real valued transform similar to the complex Fourier transform that finds numerous applications in a variety of fields including pattern recognition and signal and image processing. In this paper, we propose and study two compact and versatile hardware architectures for the computation of the 8-point, 16-point and 32-point Two-Band Fast Discrete Hartley Transform. These highly modular architectures have a symmetric and regular structure consisting of two blocks, a multiplication block and an addition/subtraction block. The first architecture utilizes 8 multipliers and 16 adders/subtractors, achieving a maximum clock frequency of 95 MHz. The second architecture utilizes only 4 multipliers and 8 adders/subtractors, achieving a maximum clock frequency of 100 MHz; however it requires additional multiplexers and more clock cycles (from 1 to 58 clock cycles depends on the points) for the computation. As a result, the proposed hardware architectures constitute an efficient choice for area-restricted applications such as embedded or pervasive computing systems.},
keywords = {Digital signal processing, FPGA architecture, Two-band fast discrete hartley transform, VHDL},
pubstate = {published},
tppubtype = {article}
}
The discrete Hartley transform is a real valued transform similar to the complex Fourier transform that finds numerous applications in a variety of fields including pattern recognition and signal and image processing. In this paper, we propose and study two compact and versatile hardware architectures for the computation of the 8-point, 16-point and 32-point Two-Band Fast Discrete Hartley Transform. These highly modular architectures have a symmetric and regular structure consisting of two blocks, a multiplication block and an addition/subtraction block. The first architecture utilizes 8 multipliers and 16 adders/subtractors, achieving a maximum clock frequency of 95 MHz. The second architecture utilizes only 4 multipliers and 8 adders/subtractors, achieving a maximum clock frequency of 100 MHz; however it requires additional multiplexers and more clock cycles (from 1 to 58 clock cycles depends on the points) for the computation. As a result, the proposed hardware architectures constitute an efficient choice for area-restricted applications such as embedded or pervasive computing systems.