2016
Pyrgas, Labros; Kitsos, Paris; Skodras, Athanassios
An FPGA design for the two-band fast discrete hartley transform Proceedings Article
In: 2016 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT), pp. 295–299, IEEE 2016.
Abstract | Links | BibTeX | Tags: Digital signal processing, Field Programmable Gate Array architecture (FPGA), Two-band fast discrete hartley transform, VHDL
@inproceedings{Pyrgas2016b,
title = {An FPGA design for the two-band fast discrete hartley transform},
author = {Labros Pyrgas and Paris Kitsos and Athanassios Skodras},
url = {https://ieeexplore.ieee.org/document/7886052},
doi = {10.1109/ISSPIT.2016.7886052},
year = {2016},
date = {2016-01-01},
booktitle = {2016 IEEE International Symposium on Signal Processing and Information Technology (ISSPIT)},
pages = {295--299},
organization = {IEEE},
abstract = {The discrete Hartley transform finds numerous applications in signal and image processing. An efficient Field Programmable Gate Array implementation for the 64-point Two-Band Fast Discrete Hartley Transform is proposed in this communication. The architecture requires 57 clock cycles to compute the 64-point Two-Band Fast Discrete Hartley Transform and reaches a rate of up to 103.82 million samples per second at a 92 MHz clock frequency. The architecture has been implemented using VHDL and realized on a Cyclone IV FPGA of Altera.},
keywords = {Digital signal processing, Field Programmable Gate Array architecture (FPGA), Two-band fast discrete hartley transform, VHDL},
pubstate = {published},
tppubtype = {inproceedings}
}
The discrete Hartley transform finds numerous applications in signal and image processing. An efficient Field Programmable Gate Array implementation for the 64-point Two-Band Fast Discrete Hartley Transform is proposed in this communication. The architecture requires 57 clock cycles to compute the 64-point Two-Band Fast Discrete Hartley Transform and reaches a rate of up to 103.82 million samples per second at a 92 MHz clock frequency. The architecture has been implemented using VHDL and realized on a Cyclone IV FPGA of Altera.